 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| OX9160 PCI Peripheral Bridge with EPP Parallel Port & 8/32 bit local bus FEATURES * * * * * * * 33MHz, 32-bit target PCI controller. Fully PCI 2.2 and PCI Power Management 1.0 compliant. 8- or 32-bit pass- through Local bus. IEEE1284 parallel port. Parallel port supports EPP mode for maximum data transfer rate to printers, removable drives etc. Most operations complete within one PCI frame (no retries). Supports shared interrupts * * * * * * * * * 12 multi-purpose I/O pins which can be configured as interrupt input pins. EEPROM interface for optional reconfiguration. Local bus operation via I/O or memory mapping. Local bus supports Intel or Motorola mode signalling. Existing driver support for common I/O solutions. On-chip oscillator. 5.0V operation. Low power CMOS. 160 TQFP package. DESCRIPTION The OX9160 is a low-cost, general purpose PCI bridge solution designed to ease the migration to PCI of parallel port cards and instrumentation devices. It is configurable to provide either a Local bus interface or a bi-directional parallel port. Using the local bus function, legacy devices can be easily accessed throught the target PCI interface, which is compliant with version 2.2 of the PCI Bus Specification and version 1.0 of PCI Power Management Specification. All reads and writes are completed with a minimum of PCI wait states, which ensures lower PCI bus occupancy than most similar PCI bridge solutions. The local bus can be configured to operate with either 8- or 32-bit data, using either Intel x86 style or Motorola style signalling. Alternatively the local bus can be disabled in favour of an integrated IEEE 1284 EPP parallel port. The parallel port is an IEEE 1284-compliant host interface, which supports SPP, PS2 (bidirectional) and EPP modes. The local Bus function is extremely flexible, allowing the designer to customize the addressable space, divide it into chip-select regions, access devices via I/O or memory space mapping, and adjust the timings of all operations. The default register values have been selected to support many standard peripheral chips such as I/O controllers and other ISA- type devices, however all such parameters can be overwritten using an optional MicrowireTM serial EEPROM. Oxford Semiconductor Ltd. 25 Milton Park, Abingdon, Oxon, OX14 4SH, UK Tel: +44 (0)1235 824900 Fax: +44(0)1235 821141 (c) Oxford Semiconductor 1999 OX9160 Data Sheet Revision 1.2 - June 2001 Part No. OX9160-TQC33- A OXFORD SEMICONDUCTOR LTD. OX9160 CONTENTS 1 2 3 4 4.1 4.2 4.2.1 4.3 4.3.1 4.3.2 4.3.3 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.5 4.6 BLOCK DIAGRAM .......................................................................................................................3 PIN INFORMATION .....................................................................................................................4 PIN DESCRIPTIONS ....................................................................................................................5 PCI TARGET CONTROLLER .......................................................................................................8 OPERATION.......................................................................................................................................................................... 8 CONFIGURATION SPACE ................................................................................................................................................... 8 PCI CONFIGURATION SPACE REGISTER MAP ........................................................................................................... 9 ACCESSING LOGICAL FUNCTIONS................................................................................................................................ 10 PCI ACCESS TO 8-BIT LOCAL BUS ............................................................................................................................. 10 PCI ACCESS TO 32-BIT LOCAL BUS ........................................................................................................................... 11 PCI ACCESS TO PARALLEL PORT .............................................................................................................................. 11 ACCESSING LOCAL CONFIGURATION REGISTERS .................................................................................................... 12 LOCAL CONFIGURATION AND CONTROL REGISTER `LCC' (OFFSET 0X00) ......................................................... 12 MULTI-PURPOSE I/O CONFIGURATION REGISTER `MIC' (OFFSET 0X04) ............................................................. 13 LOCAL BUS TIMING PARAMETER REGISTER 1 `LT1' (OFFSET 0X08): ................................................................... 14 LOCAL BUS TIMING PARAMETER REGISTER 2 `LT2' (OFFSET 0X0C): .................................................................. 16 GLOBAL INTERRUPT STATUS AND CONTROL REGISTER `GIS' (OFFSET 0X1C) ................................................ 17 PCI INTERRUPTS ............................................................................................................................................................... 18 POWER MANAGEMENT.................................................................................................................................................... 19 5 5.1 5.2 5.3 5.4 LOCAL BUS ..............................................................................................................................20 OVERVIEW.......................................................................................................................................................................... 20 OPERATION........................................................................................................................................................................ 20 CONFIGURATION & PROGRAMMING ............................................................................................................................. 21 CLOCK REFERENCES ...................................................................................................................................................... 21 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 BIDIRECTIONAL PARALLEL PORT...........................................................................................22 OPERATION AND MODE SELECTION ............................................................................................................................. 22 SPP MODE...................................................................................................................................................................... 22 PS2 MODE...................................................................................................................................................................... 22 EPP MODE...................................................................................................................................................................... 22 ECP MODE (NOT SUPPORTED)................................................................................................................................... 22 PARALLEL PORT INTERRUPT ......................................................................................................................................... 22 REGISTER DESCRIPTION................................................................................................................................................. 23 PARALLEL PORT DATA REGISTER `PDR'................................................................................................................... 23 DEVICE STATUS REGISTER `DSR'.............................................................................................................................. 23 DEVICE CONTROL REGISTER `DCR' .......................................................................................................................... 24 EPP ADDRESS REGISTER `EPPA' ............................................................................................................................... 24 EPP DATA REGISTERS `EPPD1-4' ............................................................................................................................... 24 EXTENDED CONTROL REGISTER `ECR' .................................................................................................................... 24 SPECIFICATION ................................................................................................................................................................. 25 EEPROM DATA ORGANISATION ..................................................................................................................................... 25 ZONE0: HEADER............................................................................................................................................................ 25 ZONE1: LOCAL CONFIGURATION REGISTERS ......................................................................................................... 26 ZONE2: IDENTIFICATION REGISTERS........................................................................................................................ 27 ZONE3: PCI CONFIGURATION REGISTERS ............................................................................................................... 27 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 SERIAL EEPROM......................................................................................................................25 8 9 OPERATING CONDITIONS ........................................................................................................28 DC ELECTRICAL CHARACTERISTICS ......................................................................................28 Page 2 Data Sheet Revision 1.22 OXFORD SEMICONDUCTOR LTD. 9.1 9.2 OX9160 NON-PCI I/O BUFFERS ...................................................................................................................................................... 28 PCI I/O BUFFERS............................................................................................................................................................... 29 10 10.1 10.2 AC ELECTRICAL CHARACTERISTICS ...................................................................................30 PCI BUS............................................................................................................................................................................... 30 LOCAL BUS ........................................................................................................................................................................ 30 11 12 13 TIMING WAVEFORMS............................................................................................................32 PACKAGE INFORMATION .....................................................................................................37 ORDERING INFORMATION ....................................................................................................37 1 BLOCK DIAGRAM LBA[7:0] LBD[7:0] Local Bus AD[31:0] C/BE[3:0]# CLK FRAME# Internal Data / control bus DEVSEL# IRDY# TRDY# STOP# PAR SERR# PERR# IDSEL RST# INTA# PCI interface PD[7:0] ACK# PE BUSY Parallel port SLCT ERR# SLIN# INIT# AFD# STB# LBCS[3:0] LBWR# LBRD# LBRST MODE[1:0] Config. interface PME# Interrupt logic EEPROM interface XTALI XTALO UART_Ck_Out Crystal Oscillator LBCLK MIO[11:0] EE_DO EE_DI EE_CK EE_CS Figure 1 : OX9160 block diagram Data Sheet Revision 1.22 Page 3 OXFORD SEMICONDUCTOR LTD. OX9160 2 PIN INFORMATION Mode `00': 8-bit local bus LBA1 LBA2 LBA3 LBCS0# LBCS1# LBCS2# LBCS3# LBRD# LBWR# VDD GND LBCLK LBA4 LBA5 LBA6 LBA7 VDD GND LBDOUT LBD0 LBD1 LBD2 LBD3 VDD GND LBD4 LBD5 LBD6 LBD7 MIO8 MIO9 MIO10 MIO11 GND GND GND GND GND NC NC LBA0 LBRST LBRST# MIO7 MIO6 MIO5 MIO4 MIO3 MIO2 MIO1 MIO0 INTA# NC RST# GND CLK VDD PME# AD31 AD30 AD29 GND AD28 AD27 AD26 GND VDD AD25 AD24 C/BE3# IDSEL AD23 GND AD22 AD21 AD20 VDD GND AD19 AD18 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 OX9160-TQC33-A NC NC NC NC GND GND GND GND VDD XTL_Ck_Out GND GND GND GND GND VDD XTLO XTLI GND GND GND NC NC VDD GND NC NC NC NC GND GND GND GND GND GND Mode0 Mode1 NC EE_DI EE_CK Mode `01': Parallel port BUSY SLCT ERR# NC NC NC NC NC NC VDD GND NC SLIN# INIT# AFD# STB# VDD GND NC PD0 PD1 PD2 PD3 VDD GND PD4 PD5 PD6 PD7 MIO8 MIO9 MIO10 MIO11 GND GND GND GND GND NC NC PE ACK# NC MIO7 MIO6 MIO5 MIO4 MIO3 MIO2 MIO1 NC INTA# NC RST# GND CLK VDD PME# AD31 AD30 AD29 GND AD28 AD27 AD26 GND VDD AD25 AD24 C/BE3# IDSEL AD23 GND AD22 AD21 AD20 VDD GND AD19 AD18 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 Mode `11': 32-bit local bus LBA1 LBA2 LBA3 LBCS0# LBCS1# LBCS2# LBCS3# LBRD# LBWR# VDD GND LBCLK LBA4 LBA5 LBA6 LBA7 VDD GND LBDOUT LBD0 LBD1 LBD2 LBD3 VDD GND LBD4 LBD5 LBD6 LBD7 MIO8 MIO9 MIO10 MIO11 LBD8 LBD9 LBD10 LBD11 LBD12 LBD13 LBD14 OX9160-TQC33-A LBA0 LBRST LBRST# MIO7 MIO6 MIO5 MIO4 MIO3 MIO2 MIO1 MIO0 INTA# NC RST# GND CLK VDD PME# AD31 AD30 AD29 GND AD28 AD27 AD26 GND VDD AD25 AD24 C/BE3# IDSEL AD23 GND AD22 AD21 AD20 VDD GND AD19 AD18 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 OX9160-TQC33-A 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 LBD15 LBA8 LBA9 LBA10 LBA11 NC NC NC VDD XTL_Ck_Out GND NC LBD16 LBD17 LBD18 VDD XTLO XTLI GND LBD19 LBD20 LBD21 LBD22 VDD GND LBD23 LBD24 LBD25 LBD26 LBD27 LBD28 LBD29 LBD30 LBD31 GND Mode0 Mode1 NC EE_DI EE_CK NC NC NC NC GND GND GND GND VDD NC GND GND GND GND GND VDD NC NC GND GND GND NC NC VDD GND NC NC NC NC GND GND GND GND GND GND Mode0 Mode1 NC EE_DI EE_CK 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL# GND STOP# PERR# SERR# PAR C/BE1# AD15 AD14 AD13 GND VDD AD12 AD11 GND VDD AD10 AD9 GND AD8 C/BE0# AD7 AD6 GND VDD AD5 AD4 AD3 GND AD2 AD1 AD0 EE_CS EE_DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Data Sheet Revision 1.22 AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL# GND STOP# PERR# SERR# PAR C/BE1# AD15 AD14 AD13 GND VDD AD12 AD11 GND VDD AD10 AD9 GND AD8 C/BE0# AD7 AD6 GND VDD AD5 AD4 AD3 GND AD2 AD1 AD0 EE_CS EE_DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Figure 2: Pinout in all configurable modes (package = 160 TQFP) AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL# GND STOP# PERR# SERR# PAR C/BE1# AD15 AD14 AD13 GND VDD AD12 AD11 GND VDD AD10 AD9 GND AD8 C/BE0# AD7 AD6 GND VDD AD5 AD4 AD3 GND AD2 AD1 AD0 EE_CS EE_DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Page 4 OXFORD SEMICONDUCTOR LTD. OX9160 3 PIN DESCRIPTIONS 11 Dir Name Description Mode 00 01 PCI Interface 139, 140, 141, 143, 144, 145, 148, 149, 152, 154, 155, 156, 159, 160, 1, 2, 14, 15, 16, 19, 20, 23, 24, 26, 28, 29, 32, 33, 34, 36, 37, 38 P_I/O AD[31:0] Multiplexed PCI Address/Data bus 150, 3, 13, 27 136 4 7 5 6 9 12 11 10 151 134 132 138 Local bus 122 N/A 122 123 N/A 123 102 114-7 112 113 105-8 118-21 P_I P_I P_I P_O P_I P_O P_O P_I/O P_O P_I/O P_I P_I P_OD P_OD O O O O O O O O Z O O I/O I/O C/BE[3:0]# CLK FRAME# DEVSEL# IRDY# TRDY# STOP# PAR SERR# PERR# IDSEL RST# INTA # PME# LBRST LBRST# LBDOUT LBCS[3:0]# LBDS[3:0]# LBWR# LBRDWR# LBRD# Hi-Z LBA[7:0] LBA[12:0] LBD[7:0] LBD[31:0] PCI Command/Byte enable PCI system clock Cycle Frame Device Select Initiator ready Target ready Target Stop request Parity System error Parity error Initialization device select PCI system reset PCI interrupt Power management event Local bus active-high reset Local bus active-low reset Local bus data out enable. This pin can be used by external transceivers; it is high when LBD[7:0] are in output mode and low when they are in input mode. Local bus active-low Chip-Select (Intel mode) Local bus active-low Data-Strobe (Motorola mode) Local bus active-low write-strobe (Intel mode) Local bus Read-not- Write control (Motorola mode) Local bus active-low read-strobe (Intel mode) Permanent high impedance (Motorola mode) (8-bit mode) Local bus address signals (32-bit mode) Local bus address signals (8-bit mode) Local bus data signals (32-bit mode) Local bus data signals N/A N/A N/A N/A N/A N/A N/A 114-7 112 113 N/A 76-9, 105-8, 118-21 N/A 92-5 98-101 N/A 47-55, 58-61, 66-68, 80-87, 92-95, 98-101 N/A Data Sheet Revision 1.22 Page 5 OXFORD SEMICONDUCTOR LTD. OX9160 Parallel port N/A 122 N/A N/A N/A N/A N/A N/A N/A N/A 121 120 108 119 118 107 106 105 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A I I I OD I I OD OD OD I/O O O IU O I O O O I ACK# PE BUSY SLIN# SLCT ERR# INIT# AFD# STB# PD[7:0] EE_CK EE_CS EE_DI EE_DO XTLI XTLO XTL_Ck_Out LBCLK Mode[1:0] N/A Bus EEPROM pins 41 39 42 Acknowledge (SPP mode). ACK# is asserted (low) by the peripheral to indicate that a successful data transfer has taken place. Paper Empty. Activated by printer when it runs out of paper. Busy (SPP mode). BUSY is asserted (high) by the peripheral when it is not ready to accept data Select (SPP mode). Asserted by host to select the peripheral Peripheral selected. Asserted by peripheral when selected. Error. Held low by the peripheral during an error condition. Initialize (SPP mode). Commands the peripheral to initialize. Auto Feed (SPP mode, open-drain) Strobe (SPP mode). Used by peripheral to latch data currently available on PD[7:0] Parallel data bus EEPROM clock EEPROM active-high Chip Select EEPROM data in. When the serial EEPROM is connected, this pin should be pulled up using 1-10k resistor. When the EEPROM is not used the internal pullup is sufficient. EEPROM data out. Crystal oscillator input Crystal oscillator output. Maximum frequency 60MHz Buffered crystal clock output. This clock can drive TTL clock signals from a clock generator circuit connected at XTLI & XTLO. Can be enabled/disabled by software. Buffered PCI clock. Can be enabled/disabled by software Mode selector: 00: 8-bit local bus 01: Parallel port 11: 32-bit local bus 40 Miscellaneous pins 63 64 71 109 44,45 Power & Ground 18, 31, 57, 72, 97, 111, 147, 157 22, 65, 104, 137 8, 17, 25, 30, 35, 56, 70, 96, 110, 142, 146, 153, 158 21, 46, 47, 48, 49, 50, 51, 60, 61, 62, 66, 67, 68, 69, 73, 74, 75, 76, 83, 84, 85, 86, 87, 103, 135, V V G G AC VDD DC VDD AC GND DC GND Supplies power to output buffers in switching (AC) state Power supply. Supplies power to core logic, input buffers and output buffers in steady state Supplies GND to output buffers in switching (AC) state Ground (0 volts). Supplies GND to core logic, input buffers and output buffers in steady state Table 1: Pin Descriptions Data Sheet Revision 1.22 Page 6 OXFORD SEMICONDUCTOR LTD. OX9160 Multi-purpose & External interrupt pins 131 N/A 131 I/O MIO0 N/A 131 130 129 N/A Z I/O I/O I 124-128 Multi-purpose I/O 0. Can drive high or low, or assert a PCI interrupt Permanent high impedance Multi-purpose I/O 1. Can drive high or low, or assert a PCI interrupt. Multi-purpose I/O 2. When LCC[7] = 0, this pin can drive high or low, or assert a PCI interrupt. Input power management event. When LCC[7] is set this input pin can assert a function1 PME# Multi-purpose I/O pins. Can drive high or low, or assert a PCI interrupt Hi-Z MIO1 MIO2 PME_In MIO[11:3] 88-91 124-128 88-91 124-128 88-91 I/O Note 1: Direction key: I IU O I/O OD NC Z Input Input with internal pull-up Output Bi-directional Open drain No connect High impedance P_I P_O P_I/O P_OD G V PCI input PCI output PCI bi-directional PCI open drain Ground 5.0V power Note 2: Power & Ground There are two GND and two VDD rails inside the device. One set of rails supply power and ground to output buffers while in switching state (called AC power) and another rail supply the core logic, input buffers and output buffers in steady-state (called DC rail). The rails are not connected internally. This precaution reduces the effects of simultaneous switching outputs and undesirable RF radiation from the chip. Further precaution is taken by segmenting the GND and VDD AC rails to isolate the PCI, Local bus and parallel port pins. Also, some GND pins (italicised) serve as GND in mode `00' and mode `01'; however they are multiplexed and function as address/data pins in mode `11'. Data Sheet Revision 1.22 Page 7 OXFORD SEMICONDUCTOR LTD. OX9160 4 4.1 PCI TARGET CONTROLLER Operation The OX9160 will complete all transactions as disconnectwith-data, ie the device will assert the STOP# signal alongside TRDY#, to ensure that the Bus Master does not continue with a burst access. The exception to this is Retry, which will be signalled in response to any access while the OX9160 is reading from the serial EEPROM. The OX9160 performs medium- speed address decoding as defined by the PCI specification. It asserts the DEVSEL# bus signal two clocks after FRAME# is first sampled low on all bus transaction frames which address the chip. Fast back- to-back transactions are supported by the OX9160 as a target, so a bus master can perform faster sequences of write transactions to the Local bus when an inter-frame turn-around cycle is not required. The device supports any combination of byte-enables to the PCI Configuration Registers, the Local Configuration registers (see Base Address 2 and 3) and the Local bus controller in 32-bit mode. If a byte-enable is not asserted, that byte is unaffected by a write operation and undefined data is returned upon a read. The OX9160 performs parity generation and checking on all PCI bus transactions as defined by the standard. If a parity error occurs during the PCI bus address phase, the device will report the error in the standard way by asserting the SERR# bus signal. However if that address/command combination is decoded as a valid access, it will still complete the transaction as though the parity check was correct. The OX9160 responds to the following PCI transactions:* Configuration access: The OX9160 responds to type 0 configuration reads and writes if the IDSEL signal is asserted and the bus address is selecting a valid configuration register. The device will respond to the configuration transaction by asserting DEVSEL#. Data transfer then follows. Any other configuration transaction will be ignored by the OX9160. IO reads/writes: The address is compared with the addresses reserved in the I/O Base Address Registers (BARs). If the address falls within one of the assigned ranges, the device will respond to the IO transaction by asserting DEVSEL#. Data transfer follows this address phase. For the parallel port and 8-bit Local bus functions, only byte accesses are supported; however the 32-bit bridge function also supports word and dword accesses. For IO accesses to these regions, the controller compares AD[1:0] with the byteenable signals as defined in the PCI specification. The access is always completed; however if the correct BE signal is not present the transaction will have no effect Memory reads/writes: These are treated in the same way as I/O transactions, except that the memory ranges are used. Memory access to single-byte regions is always expanded to DWORDs in the OX9160. In other words, OX9160 reserves a DWORD per byte in single-byte regions. The device allows the user to define the active byte lane using LCC[4:3] so that in Big-Endian systems the hardware can swap the byte lane automatically. For Memory mapped access in single-byte regions, the OX9160 compares the asserted byte-enable with the selected byte-lane in LCC[4:3] and completes the operation if a match occurs, otherwise the access will complete normally on the PCI bus, but it will have no effect on the actual controller. All other cycles (64-bit, special cycles, reserved encoding etc.) are ignored. * * 4.2 Configuration space configuration space Power Management The format of the 2 overleaf. All required fields in the standard header are implemented, plus the Extended Capability register set. configuration space is shown in Table In general, writes to any registers that are not implemented are ignored, and all reads from unimplemented registers return 0. * Data Sheet Revision 1.22 Page 8 OXFORD SEMICONDUCTOR LTD. OX9160 4.2.1 31 PCI Configuration Space Register map 16 Configuration Register Description 15 0 Class Code Revision ID Header Type Reserved Reserved Base Address Register 0 (BAR0) Base Address Register 1 (BAR 1) Base Address Register 2 (BAR 2) - Local Configuration Registers in IO space Base Address Register 3 (BAR3) - Local Configuration Registers in Memory space Reserved Reserved Reserved Subsystem ID Subsystem Vendor ID Reserved Reserved Cap_Ptr Reserved Reserved Reserved Interrupt Pin Interrupt Line Power Management Capabilities (PMC) Next Ptr Cap_ID Reserved Reserved PMC Control/Status Register (PMCSR) BIST 1 Table 2: PCI Configuration space Register name Vendor ID Device ID Command Status Revision ID Class code Header type BAR 0 BAR 1 BAR 2 BAR 3 Subsystem VID Subsystem ID Cap ptr. Interrupt line Interrupt pin Cap ID Next ptr. PM capabilities PMC control/ status register Reset value 32-bit local bus 0x1415 0x9512 0x0000 0x0290 0x00 0x068000 0x80 0x00000001 0x00000000 0x00000001 0x00000000 0x1415 0x0000 0x40 0x00 0x01 0x01 0x00 0x6C01 0x0000 Device ID Status Vendor ID Command Offset Address 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 8-bit local bus 0x9511 Parallel port 0x9513 0x068000 0x070101 Program read/write EEPROM PCI W R W R R/W W (bit 4) R/W R W R R R/W R/W R/W R/W W R W R R R/W R R R W R R/W Table 3: PCI configuration space default values Data Sheet Revision 1.22 Page 9 OXFORD SEMICONDUCTOR LTD. OX9160 4.3 Accessing logical functions Access to the local bus and parallel port is achieved via standard I/O and memory mapping, at addresses defined by the Base Address Registers (BARs) in configuration space. The BARs are configured by the system to allocate blocks of I/O and memory space to the logical functions, according to which function is enabled and the size required. The addresses allocated can then be used to access the functions. The mapping of these BARs is shown in Table 4. BAR 0 1 2 3 4 5 Local bus Parallel port Local bus (I/O mapped) Parallel port base registers (I/O mapped) Local bus (memory mapped) Parallel port extended registers (I/O mapped) Local configuration registers (I/O mapped) Local configuration registers (memory mapped) Unused Unused Table 4: Base Address Register definition 4.3.1 PCI access to 8-bit local bus BAR 0 and BAR 1 are used to access the Local bus. The system allocates a block of I/O space and a block of memory space according to the size requested. I/O space In order to minimise the usage of IO space, the block size for BAR0 (I/O access) is user definable in the range of 4 to 256 bytes. Having assigned the address range, the user can define two adjacent address bits to decode up to four chip selects internally. This facility allows glueless implementation of the local bus connecting to four external peripheral chips. The address range and the lower address bit for chip- select decoding (Lower-Address-CS-Decode) are defined in the Local bus Configuration register (see LT2[26:20] in section 1.1). The 8 Local bus has eight address lines (LBA[7:0]) -bit which correspond to the maximum IO address space. If the maximum allowable block size is allocated to the IO space (i.e. 256 bytes), then as access in IO space is byte aligned, LBA[7:0] equal PCI AD[7:0] respectively. When the user selects an address range which is less than 256 bytes, the unused upper address lines will be set to logic zero. The region can be divided into four chip-select regions when the user selects the second uppermost non-zero address bit for chip-select decoding. For example if 32bytes of IO space are reserved, the local bus address lines A[4:0] are active and the remaining address lines are set to zero. To generate four chip-selects the user should select A3 as the Lower-Address-CS-Decode. In this case A[4:3] will be used internally to decode chip-selects, asserting LBCS0# when the address offset is 00-07h, LBCS1# when offset is 08-0Fh, LBCS2# when offset is 10-17h, and LBCS3# when offset is 18- 1Fh. The region can be divided into two chip-select regions by selecting the uppermost address bit to decode chip selects. In the above example, the user can select A4 as the Lower-Address-CS-Decode, thus using A[5:4] internally to decode chip selects. As in this example LBA5 is always zero, only chip-select lines LBCS0# and LBCS1# will be decoded into, asserting LBCS0# when address offset is 000Fh and LBCS1# when offset is 10-1Fh. The region can be allocated to a single chip-select region by assigning an address bit beyond the selected range to Lower-Address-CS-Decode (but not above A8). In the above example, if the user selects A5 as the LowerAddress-CS-Decode, A[6:5] will be used to internally decode chip-selects. As in this example LBA[7:5] are always zero, only the chip select line LBCS0# may be selected. In this case address offset 00-1Fh asserts LBCS0# and the other chip-select lines remain inactive permanently. Memory Space: The memory base address registers have an allocated fixed size of 4K bytes in the address space. Since the Local bus has 8 address lines and the OX9160 only implements DWORD aligned accesses in memory space, the 256 bytes of addressable space per chip select is expanded to 1K. Unlike an I/O access, for a memory access the unused upper address lines are always active and the internal chip-select decoding logic ignores the user setting for Lower-Address-CS-Decode (LT2[26:23]) and uses PCI AD[11:10] to decode into 4 chip-select regions. When the Local bus is accessed in memory space, A[9:2] are asserted on LBA[7:0]. The chip-select regions are defined in Table 5. Data Sheet Revision 1.22 Page 10 OXFORD SEMICONDUCTOR LTD. OX9160 Local bus Chip-Select (Data-Strobe) LBCS0# (LBDS0#) LBCS1# (LBDS1#) LBCS2# (LBDS2#) LBCS3# (LBDS3#) PCI Offset from BAR 1 (Memory space) Lower Address Upper Limit 000h 3FCh 400h 7FCh 800h BFCh C00h FFCh Table 5: PCI address map for local bus (memory) Note: The description given for I/O and memory accesses is for an Intel- type configuration for the Local bus. For Motorola-type configuration, the chip select pins are redefined to data strobe pins. In this mode the Local bus offers up to 8 address lines and four data-strobe pins. Number of Chip selects 1 2 4 1 2 4 Memory block size (Kbytes) 16 16 16 4 4 4 LT2[28:27] `01' `01' `01' `00' `00' `00' LT2[26:23] `1010' `1001' `1000' `1000' `0111' `0110' Table 6: PCI access to 32-bit local bus (memory) 4.3.3 PCI access to parallel port 4.3.2 PCI access to 32-bit local bus Access to the Local bus in 32-bit mode is similar to 8-bit mode (see section 4.3.1) with the following exceptions: * The local Bus offers a 32-bit bi-directional data bus and 12 bit address bus * The PCI address signals `AD[13:2]' are asserted on LBA[11:0] * Block size in memory space is programmable by LT2[28:27] (see section 1.1) * The Lower-Address-CS-Decode (LT2[26:23]) parameter is used to decode up to 4 chip selects The block size allocation for chip-select regions is defined in Table 6. When the parallel port is enabled (Mode 01), access to the port works via BAR definitions as usual, except that there are two I/O BARs corresponding to two sets of registers defined to operate a bi-directional Parallel Port. Memory mapped access to the parallel port is not supported. The user can change the I/O space block size of BAR0 by over-writing the default values in LT2[25:20] using the serial EEPROM (see section 1.1). For example the user can reduce the allocated space for BAR0 to 4 -bytes by setting LT2[22:20] to `001'. The I/O block size allocated to BAR1 is fixed at 8-Bytes. Legacy PC parallel ports expect the upper register set to be mapped 0x400 above the base block, therefore if the BARs are fixed with this relationship, generic parallel port drivers can be used to operate the device in all modes. Example: BAR0 = 0x00000379 (8 bytes at address 0x378) BAR1 = 0x00000779 (8 bytes at address 0x778) If this relationship is not used, custom drivers will be needed. Data Sheet Revision 1.22 Page 11 OXFORD SEMICONDUCTOR LTD. OX9160 4.4 Accessing Local configuration registers The local configuration registers are a set of device specific registers which are used to configure the controller. They are mapped to the I/O and memory addresses set up in BAR2 and BAR3, with the offsets defined for each register. Access is limited to byte only for I/O accesses; memory accesses can also be word or dword accessed, however on little-endian systems such as Intel 80x86 the byte order will be reversed. 4.4.1 Local Configuration and Control register `LCC' (Offset 0x00) This register defines control of ancillary functions such as Power Management, external clock reference signals and the serial EEPROM. The individual bits are described below. Bits 1:0 2 4:3 Description Mode. These bits return the state of the Mode[1:0] pins. Enable crystal clock output. When this bit is set, the crystal oscillator output pin (XTL_Ck_Out) is active. When low, XTL_Ck_Out is permanently low. Endian Byte-Lane Select for memory access to 8-bit Local bus. 00 = Select Data[7:0] 10 = Select Data[23:16] 01 = Select Data[15:8] 11 = Select Data[31:24] Memory access to OX9160 is always DWORD aligned. When accessing 8-bit regions like the 8-bit Local bus and the parallel port, this option selects the active byte lane. As both PCI and PC architectures are little endian, the default value will be used by systems, however, some nonPC architectures may need to select the byte lane. These bits are ignored in 32-bit Local bus. Reserved. These bits are used for test purposes. The device driver must write zeros to these bits. MIO2_PME Enable. A value of `1' enables the MIO2 pin to set the PME_Status in PMCSR register, and hence assert the PME# pin if enabled. A value of `0' disables MIO2 from setting the PME_Status bit (see section 4.6). Reserved. These bits are used for test purposes. The device driver must write zeros to these bits. EEPROM Clock. For PCI read or write to the EEPROM , toggle this bit to generate an EEPROM clock (EE_CK pin). EEPROM Chip Select. When 1 the EEPROM chip-select pin EE_CS is activated (high). When 0 EE_CS is de-active (low). EEPROM Data Out. For writes to the EEPROM, this output bit is the input-data of the EEPROM. This bit is output on EE_DO and clocked into the EEPROM by EE_CK. EEPROM Data In. For reads from the EEPROM, this input bit is the output-data of the EEPROM connected to EE_DI pin. EEPROM Valid. A 1 indicates that a valid EEPROM program is present Reload configuration from EEPROM. Writing a 1 to this bit re-loads the configuration from EEPROM. This bit is self- clearing after EEPROM read Reserved Reserved EEPROM Read/Write W W PCI R RW RW Reset XX 0 00 6:5 7 W R RW 00 0 23:8 24 25 26 27 28 29 30 31 - R RW RW RW R R RW R 0000h 0 0 0 X X 0 0 0 Data Sheet Revision 1.22 Page 12 OXFORD SEMICONDUCTOR LTD. OX9160 4.4.2 Multi-purpose I/O Configuration register `MIC' (Offset 0x04) This register configures the operation of the multi-purpose I/O pins `MIO[11:0] as follows. Bits 1:0 Description MIO0 Configuration Register (Mode[1:0]`01'). 00 -> MIO0 is a non-inverting input pin 01 -> MIO0 is an inverting input pin 10 -> MIO0 is an output pin driving `0' 11 -> MIO0 is an output pin driving `1' Unused (Mode[1:0]=`01'). When t e Parallel Port is enabled, MIO[0] pin h is unused and will remain in forcing output mode. MIO1 Configuration Register 00 -> MIO1 is a non-inverting input pin 01 -> MIO1 is an inverting input pin 10 -> MIO1 is an output pin driving `0' 11 -> MIO1 is an output pin driving `1' MIO2 Configuration Register (LCC[7]='0'). 00 -> MIO2 is a non-inverting input pin 01 -> MIO2 is an inverting input pin 10 -> MIO2 is output pin driving `0' 11 -> MIO2 is output pin driving `1' PME_Input (LCC[7]='1'). When LCC[7] is set, MIO2 pin is re-defined to PME_Input. It's polarity will be controlled by MIC[4]. It sets the sticky PME_Status bit. MIO3 Configuration Register. 00 -> MIO3 is a non-inverting input pin 01 -> MIO3 is an inverting input pin 10 -> MIO3 is an output pin driving `0' 11 -> MIO3 is an output pin driving `1' MIO4 Configuration Register. 00 -> MIO4 is a non-inverting input pin 01 -> MIO4 is an inverting input pin 10 -> MIO4 is an output pin driving `0' 11 -> MIO4 is an output pin driving `1' MIO5 Configuration Register. 00 -> MIO5 is a non-inverting input pin 01 -> MIO5 is an inverting input pin 10 -> MIO5 is an output pin driving `0' 11 -> MIO5 is an output pin driving `1' MIO6 Configuration Register. 00 -> MIO6 is a non-inverting input pin 01 -> MIO6 is an inverting input pin 10 -> MIO6 is an output pin driving `0' 11 -> MIO6 is an output pin driving `1' MIO7 Configuration Register. 00 -> MIO7 is a non-inverting input pin 01 -> MIO7 is an inverting input pin 10 -> MIO7 is an output pin driving `0' 11 -> MIO7 is an output pin driving `1' MIO8 Configuration Register. 00 -> MIO8 is a non-inverting input pin EEPROM Read/Write PCI W RW Reset 00 3:2 W RW 00 5:4 W RW 00 7:6 W RW 00 9:8 W RW 00 11:10 W RW 00 13:12 W RW 00 15:14 W RW 00 17:15 W RW 00 Data Sheet Revision 1.22 Page 13 OXFORD SEMICONDUCTOR LTD. Bits Description 01 -> MIO8 is an inverting input pin 10 -> MIO8 is an output pin driving `0' 11 -> MIO8 is an output pin driving `1' MIO9 Configuration Register. 00 -> MIO9 is a non-inverting input pin 01 -> MIO9 is an inverting input pin 10 -> MIO9 is an output pin driving `0' 11 -> MIO9 is an output pin driving `1' MIO10 Configuration Register. 00 -> MIO10 is a non- inverting input pin 01 -> MIO10 is an inverting input pin 10 -> MIO10 is an output pin driving `0' 11 -> MIO10 is an output pin driving `1' MIO11 Configuration Register. 00 -> MIO11 is a non- inverting input pin 01 -> MIO11 is an inverting input pin 10 -> MIO11 is an output pin driving `0' 11 -> MIO11 is an output pin driving `1' Reserved Read/Write PCI OX9160 Reset EEPROM 19:18 W RW 00 21:20 W RW 00 23:22 W RW 00 31:24 - R 00h 4.4.3 Local bus Timing Parameter register 1 `LT1' (Offset 0x08): The Local bus Timing Parameter registers (LT1 and LT2) define the operation and timing parameters used by the Local bus. The timing parameters are programmed in 4-bit registers to define the assertion/de-assertion of the Local bus control signals. The value programmed in these registers defines the number of PCI clock cycles after a Reference Cycle when the events occur, where the reference Cycle is defined as two clock cycles after the master asserts the IRDY# signal. The following arrangement provides a flexible approach for users to define the desired bus timing of their peripheral devices. The timings refer to I/O or Memory mapped access to BAR0 and BAR1 respectively. Bits 3:0 Description Read Chip-select Assertion (Intel-type interface). Defines the number of clock cycles after the Reference Cycle when the LBCS[3:0]# pins are asserted (low) during a read operation from the Local bus.1 These bits are unused in Motorola- type interface. Read Chip-select De-assertion (Intel-type interface). Defines the number of clock cycles after the Reference Cycle when the LBCS[3:0]# pins are de-asserted (high) during a read from the Local bus. 1 These bits are unused in Motorola- type interface. Write Chip-select Assertion (Intel- type interface). Defines the number of clock cycles after the Reference Cycle when the LBCS[3:0]# pins are asserted (low) during a write operation to the Local bus. 1 These bits are unused in Motorola- type interface. Data Sheet Revision 1.22 Page 14 EEPROM Read/Write W PCI RW Reset 0h 7:4 W RW 3h (2h for parallel port) 0h 11:8 W RW OXFORD SEMICONDUCTOR LTD. Bits 15:12 Description Write Chip-select De-assertion (Intel- type interface). Defines the number of clock cycles after the reference cycle when the LBCS[3:0]# pins are de-asserted (high) during a write operation to the Local bus. 1 Read-not- Write De-assertion during write cycles (Motorola- type interface). Defines the number of clock cycles after the reference cycle when the LBRDWR# pin is de-asserted (high) during a write to the Local bus. 1 Read Control Assertion (Intel-type interface). Defines the number of clock cycles after the Reference Cycle when the LBRD# pin is asserted (low) during a read from the Local bus. 1 Read Data-strobe Assertion (Motorola- type interface). Defines the number of clock cycles after the Reference Cycle when the LBDS[3:0]# pins are asserted (low) during a read from the Local bus. 1 Read Control De-assertion (Intel- type interface). Defines the number of clock cycles after the Reference Cycle when the LBRD# pin is deasserted (high) during a read from the Local bus. 1 Read Data-strobe De-assertion (Motorola- type interface). Defines the number of clock cycles after the Reference Cycle when the LBDS[3:0]# pins are de-asserted (high) during a read from the Local bus. 1 Write Control Assertion (Intel- type interface). Defines the number of clock cycles after the Reference Cycle when the LBWR# pin is asserted (low) during a write to the Local bus. 1 Write Data-strobe Assertion (Motorola-type interface). Defines the number of clock cycles after the Reference Cycle when the LBDS[3:0]# pins are asserted (low) during a write to the Local bus. 1 Write Control De-assertion (Intel-type interface). Defines the number of clock cycles after the Reference Cycle when the LBWR# pin is deasserted (high) during a write to the Local bus. 1 Write Data-strobe De-assertion (Motorola- type interface). Defines the number of clock cycles after the Reference Cycle when the LBDS[3:0]# pins are de-asserted (high) during a write cycle to the Local bus. 1 Note 1: OX9160 Read/Write W Reset 2h EEPROM PCI RW 19:16 W RW 0h (1h for parallel port) 23:20 W RW 3h (2h for parallel port) 27:24 W RW 0h (1h for parallel port) 31:28 W RW 2h Only values in the range of 0h to Ah (0-10 decimal) are valid. Other values are reserved. These parameters apply to both 8-bit and 32-bit Local bus configurations. See notes in the following page. Data Sheet Revision 1.22 Page 15 OXFORD SEMICONDUCTOR LTD. OX9160 4.4.4 Bits 3:0 7:4 11:8 15:12 19:16 22:20 Local bus Timing Parameter register 2 `LT2' (Offset 0x0C): Description Write Data Bus Assertion. This register defines the number of clock cycles after the Reference Cycle when the LBD pins actively drive the data bus during a write operation to the Local bus. 1 Write Data Bus De-assertion. This register defines the number of clock cycles after the Reference Cycle when the LBD pins go high-impedance during a write operation to the Local bus. 1,2 Read Data Bus Assertion. This register defines the number of clock cycles after the Reference Cycle when the LBD pins actively drive the data bus at the end of a read operation from the Local bus. 1 Read Data Bus De-assertion. This register defines the number of clock cycles after the Reference Cycle when the LBD pins go high-impedance during at the beginning of a read cycle from the Local bus. 1 Reserved. IO Space Block Size of BAR 0. 000 = Reserved 100 = 32 Bytes 001 = 4 Bytes 101 = 64 Bytes 010 = 8 Bytes 110 = 128 Bytes 011 = 16 Bytes 111 = 256 Bytes Local bus Chip-select Parame ter `Lower-Address-CS-Decode'. 2 IO space in 8-bit Local bus Memory space and IO space in 32-bit Local bus 0000 = A2 1000 = Res 0000 = A4 1000 = A12 0001 = A3 1001 = Res 0001 = A5 1001 = A13 0010 = A4 1010 = Res 0010 = A6 1010 = A14 0011 = A5 1011 = Res 0011 = A7 1011 = Res 0100 = A6 1100 = Res 0100 = A8 1100 = Res 0101 = A7 1101 = Res 0101 = A9 1101 = Res 0110 = A8 1110 = Res 0110 = A10 1110 = Res 0111 = A9 1111 = Res 0111 = A11 1111 = Res Memory Space Block Size of BAR1 (32-bit Local bus only). 00 = 4 Kbytes 01 = 16 Kbytes 10 = Reserved 11 = Reserved EEPROM Read/Write W W W W W PCI RW RW RW RW R R Reset 0h Fh 4h (2h for parallel port) 0h 0h `100' (=`010' for parallel port) `0001' (=`0010' for parallel port) 26:23 W RW 28:27 W R 00 29 30 31 When 8-bit Local bus or Parallel Port is selected (Mode[1:0]=`00' or `01'), the Memory Block size is fixed at 4K and these bits are ignored. Local bus Software Reset. When this bit is a 1 the Local bus reset pin is activated. When this bit is a 0 the Local bus reset pin is de-activated. 3 Local bus Clock Enable. When this bit is a 1 the Local bus clock (LBCK) pin is enabled. When this bit is a 0 LBCK pin is permanently low. The Local bus Clock is a buffered PCI clock. Bus Interface Type. When low (=0) the Local bus is configured to Inteltype operation, otherwise it is configured to Motorola- type operation. Note that when Mode[1:0] is `01', this bit is hard wired to 0. W W RW RW RW 0 0 0 Note 1: Note 2: Note 3: Only values in the range of 0 to Ah (0-10 decimal) are valid. Other values are reserved as writing higher values causes the PCI interface to retry all accesses to the Local bus as it is unable to complete the transaction in 16 PCI clock cycles. The Lower-Address-CS-Decode parameter is described in sections 4.3.1 & 4.3.2. These bits are unused for Memory access to the 8-bit Local bus which uses a fixed decoding to allocate 1K regions to 4 chip selects. For further information on the Local bus, see section 5. The Local bus and the Parallel Port are both reset with PCI reset. In Addition, the user can issue the Software Reset Command. Data Sheet Revision 1.22 Page 16 OXFORD SEMICONDUCTOR LTD. OX9160 LT2[15:0] enable the card designer to control the data bus during the idle periods. The default values will configure the Local bus data pins to remain forcing (LT2[7:4] = Fh). LT[15:8] is programmed to place the bus in high-impedance at the beginning of a read cycle and set it back to forcing at the end of the read cycle. For systems that require the data bus to stay in highimpedance, the card designer should write an appropriate value in the range of 0h to Ah to LT2[7:4]. This will place the data bus in high impedance at the end of the write cycle. Whenever the value programmed in LT2[7:4] does not equal Fh, the Local bus controller will ignore the setting of LT2[15:8] as the data bus will be high-impedance outside write cycles. In this case the card designer should place external pull-ups on the data bus pins LBD[7:0] (or LBD[32:0] in 32-bit mode). While the configuration data is read from the external EEPROM, the LBD pins remain in the high-impedance state. The timing registers define the Local bus timing parameters based on signal changes relative to a reference cycle which is defined as two PCI clock cycles after IRDY# is asserted for the first time in a frame. The following parameters are fixed relative to the reference cycle. The Local bus address pins (LBA[7:0] in 8-bit Local bus, LBA[15:0] in 32-bit Local bus) are asserted during the reference cycle. In a write operation, the Local bus data is available during the reference c ycle, however I/O buffers change direction as programmed in LT2[3:0]. In a Motorola type bus write operation, the Read-not- Write pin (LBRDWR#) is asserted (low) during the reference cycle. In a read cycle this pin remains high throughout the duration of the operation. The default settings in LT1 & LT2 registers provide one PCI clock cycle for address and chip-select to control signal set- up time, one clock cycle for address and chip-select from control signal hold time, two clock cycles of pulse duration for read and write control signals and one clock cycle for data bus hold time. These parameters are acceptable for using external OX16C950, OX16C952 and OX16C954 devices connected to the Local bus, in Intel mode. Some redefinition will be required if the bus is to be operated in Motorola mode. The user should take great care when programming the Local bus timing parameters. For example defining a value for chipselect assertion which is larger that the value defined for chip- select de-assertion or defining a chip-select assertion value which is greater than control signal assertion will result in obvious invalid local Bus cycles. 4.4.5 Bits 3:0 4 Global Interrupt Status and Control Register `GIS' (Offset 0x1C) Description Reserved MIO0 (Mode[1:0]`01'). This bit reflects the state of the internal MIO[0]. The internal MIO[0] reflects the non-inverted or inverted state of MIO0 pin.1 Parallel Port Interrupt (Mode[1:0]=`01'). This bit reflects the state of the Parallel Port internal interrupt line. These bits reflect the state of the internal MIO[11:2]. The internal MIO[11:2] reflect the non-inverted or inverted state of MIO[11:2] pins respectively.1 Reserved. MIO[0] Interrupt Mask (Mode[1:0]`01'). When set (=1) this bit enables MIO0 pin to assert a PCI interrupt. When cleared (=0) it prevents MIO0 pin from asserting a PCI interrupt. 1 Parallel Port Interrupt Mask (Mode[1:0]=`01'). When set (=1) this bit enables the Parallel Port to assert a PCI interrupt. When cleared (=0) it prevents the Parallel Port from asserting a PCI interrupt. MIO Interrupt Mask. When set (=1) these bits enable each MIO[11:1] pin to assert a PCI interrupt respectively. When cleared (=0) they prevent the respective pins from asserting a PCI interrupt. 1 Read/Write EEPROM Reset PCI R R 0x0h X - 15:5 19:16 20 W R R R RW 0 XXXh Fh 1 W W RW RW 1 7FFh 31:21 Note 1: The returned value is either the direct state of the corresponding MIO pin or its inverse as configured by the Multi-purpose I/O Configuration register `MIC' (offset 0x14). As the internal MIO can assert a PCI interrupt, the inversion feature can define each external interrupt to be defined as active-low or active-high, as controlled by the MIC register. Data Sheet Revision 1.22 Page 17 OXFORD SEMICONDUCTOR LTD. OX9160 4.5 PCI Interrupts Interrupts in PCI systems are level-sensitive and can be shared. Interrupts can be triggered by the Parallel port, or from the MIO pins when using the Local bus function. The Parallel Port and MIO0 share the same interrupt status bit (GIS[4]). All interrupts in the OX9160 are routed to the PCI interrupt pin, INTA#. During the system initialisation process and PCI device configuration, system-specific software reads the interrupt pin field to determine which (if any) interrupt pin is used by each function. It programmes the system interrupt router to logically connect this PCI interrupt pin to a system-specific interrupt vector (IRQ). It then writes this routing information to the Interrupt Line field in the function's PCI configuration space. Device driver software must then hook he interrupt using the information in the t Interrupt Line field. Interrupt status for all the sources of interrupt is available using the GIS register in the Local Configuration Register set, which can be accessed using I/O or Memory operations. This facility allows a device driver to quickly ascertain the source of interrupt and service it. The OX9160 also offers additional interrupt masking ability using GIS[31:20] (see section 4.4.5), allowing drivers to temporarily disable certain sources of interrupts All interrupts can be enabled / disabled individually using the GIS register set in the Local configuration registers. When an MIO pin is enabled, an external device can assert a PCI interrupt by driving that pin. The sense of the MIO external interrupt pins (active-high or active-low) is defined in the MIC register. The parallel port can also assert an interrupt (Note: this effectively disables the MIO[0] interrupt). Data Sheet Revision 1.22 Page 18 OXFORD SEMICONDUCTOR LTD. OX9160 changes the power-state to state D2 or D3, the device takes the following actions:* * * * The external XTL_Ck_Out pin is disabled regardless of the programmed value in LCC[2]. The Local bus clock pin, LBCK, is disabled regardless of the programmed value in LT2[30]. The PCI interrupt is disabled. Access to I/O or Memory BARs is disabled. 4.6 Power Management The OX9160 is compliant with PCI Power Management Specification Revision 1.0. The local bus can recognise power states D0, D2 and D3. Power management is accomplished by power-down and power-up requests, asserted via interrupts and the PME# pin respectively. The device can assert to the PME# pin to request that the system `wake up.' The PME# pin is de-asserted when the sticky PME_Status bit is cleared. Power-down request is not defined by Power Management 1.0. It is a device-specific feature and requires a bespoke device driver implementation. The PME# pin can, in certain cases, activate the PME# signal when power is removed from the device, which will cause the PC to wake up from Low-power state D3(cold). To ensure full cross-compatibility with systemboard implementations, use of an isolator FET is recommended. If Power Management capabilities are not required, the PME# pin can be treated as no-connect. The power-down request for the Local bus is applicationdependent. The device driver can use any of the multipurpose I/O lines, MIO[12:3] to issue a power-down request. The Local bus implements the PCI Power Management power-states D0, D2 and D3. Whenever the device driver However, access to the configuration space is still enabled. The device driver can optionally assert/de-assert any of its selected (design dependant) MIO pins to switch off VCC, disable other external clocks, or activate shut- down modes to any external devices on the Local bus. Devices on the local bus can issue a wake up request by using the MIO2 pin. When LCC[7] is set, a rising or falling edge of MIO2 will cause the OX9160 to issue a wake up request by setting PME_Status = (PMCSR[15]), if it is enabled by PMCSR[8]. When LCC[7] is set, the MIO2 pin will remain in input mode regardless of the value programmed in MIC[5], However MIC[4] still controls the input sense. PME_Status is a sticky bit which will be cleared by writing a `1' to it. While the PME_En (PMCSR[8]) bit is set, PME_Status will assert the PME# pin to inform the device driver that a power management wake up event has occurred. After a wake up event is signalled, the device driver is expected to return the function to the D0 power-state. Settings for wake up events are shown in Table 7. MIO2 Falling X X X Yes No PME_Status Remains unchanged Gets set Remains unchanged Gets set Remains unchanged LCC[7] 0 1 1 1 1 MIC[4] X 0 0 1 1 MIO2 Rising X yes no X X Table 7: Local bus Wake-up configuration Data Sheet Revision 1.22 Page 19 OXFORD SEMICONDUCTOR LTD. OX9160 5 5.1 LOCAL BUS Overview strobe LBWR#, in Intel- type interfaces. For Motorola- type interfaces, LBWR# is re-defined to perform read/write control signal (LBRDWR#) and the chip-select signals (LBCS[3:0]#) are re-defined to data-strobe (LBDS[3:0]#). A reference cycle is defined, as two PCI clock cycles after the master asserts the IRDY# signal for the first time within a frame. In general, all the local bus control signals change state in the first cycle after the reference cycle, with offsets to provide suitable setup and hold times for common peripheral devices. However, all the timings can be increased / decreased independently in multiples of PCI clock cycles. This feature enables the card designer to override the length of read or write operations, the address and chip-select set- up and hold timing, and the data bus hold timing so that add-in cards can be configured to suit different speed peripheral devices connected to the Local bus. The designer can also program the data bus to remain in the high impedance state or actively drive the bus during idle periods. The local bus will always return to an idle state, where no chip-select (data-strobe in Motorola mode) signal is active, between adjacent accesses. During read cycles the local bus interface latches data from the bus on the rising edge of the clock where LBRD# (LBDS[3:0]# in Motorola mode) goes high. Card designers should ensure that their peripherals provide the OX9160 with the specified data setup and hold times with respect to this clock edge. The local bus cannot accept burst transfers from the PCI bus. If a burst transfer is attempted the PCI interface will signal 'disconnect with data' on the first data phase. The local bus does accept 'fast back- to-back' transactions from PCI. A PCI target must complete the transaction within 16 PCI clock cycles from assertion of the FRAME# signal, otherwise it should signal a retry. During a read operation from the Local bus, OX9160 waits for master-ready signal (IRDY#) and computes the number of remaining cycles to the de-assertion of the read control signal. If the total number of PCI clock cycles for that frame is greater h an t 16 clock cycles, OX9160 will post a retry. The master would normally return immediately and complete the operation in the following frame. The OX9160 incorporates a bridge from PCI to the Local bus. It allows card developers to easily migrate legacy soluations to PCI. When Mode[1:0] is `00', the Local bus is comprised of a bidirectional 8-bit data bus, an 8-bit address bus, up to four chip selects, and a number of control signals that allow for easy interfacing to standard peripherals. It also provides twelve active-high or active-low interrupt inputs. When Mode[1:0] is `11', the Local bus is comprised of a bidirectional 32-bit data bus, a 12-bit address bus, up to four chip selects, and the same control signals and interrupts as in 8-bit mode. The local bus is configured by LT1 and LT2 (see sections 4.4.3 & 4.4.4) in the Local Configuration Register space. By programming these registers the card developer can alter the characteristics of the local bus to suit the characteristics of the peripheral devices being used. 5.2 Operation The local bus can be accessed via I/O and memory space, at addresses defined by BAR 0 and BAR 1 of configuration space. The mapping to the devices will vary with the application, but the bus is fully configurable to facilitate simple development. The operation of the local bus is synchronised to the PCI bus clock. A buffered PCI clock signal is output on pin LBCLK if it has been enabled by setting LT2[30]. The eight bit bi-directional pins LBD[7:0] (LBD[31:0] in 32bit mode) drive the output data onto the bus during local bus write cycles. For reads, the device latches the data read from these pins at the end of the cycle. The local bus address is placed on pins LBA[7:0] (LBA[11:0] in 32-bit mode) at the start of each local bus cycle and will remain latched until the start of the subsequent cycle. If the maximum allowable block size (256 bytes) is allocated to the local bus in I/O space, then as access in I/O space is byte aligned, AD[7:0] are asserted on LBA[7:0]. If a smaller address range is selected, the corresponding upper address lines will be set to logic zero. The control bus is comprised of up to four chip-select signals LBCS[3:0]#, a read strobe LBRD# and a write Data Sheet Revision 1.22 Page 20 OXFORD SEMICONDUCTOR LTD. OX9160 5.3 Configuration & Programming 5.4 Clock references The configuration registers for the local bus controller are described in sections 4.4.3 & 4.4.4. The values of these registers after reset allow the host system to identify the function and configure its base address registers. Alternatively many of the default values can be reprogrammed during device initialisation through use of the optional serial EEPROM (see section 7). The I/O space block can be varied in size from 4 bytes to 256 bytes (32 bytes is the default) by setting LT2[22:20] accordingly. Varying the block size means that I/O space can be allocated efficiently by the system, whatever the application. The I/O block can then be divided into one, two or four chip-select regions, depending on the setting in LT2[26:23]. To divide the area into four chip-select region, the user should select the second uppermost non-zero address bit as the Lower-Address-CS-decode. To divide into two regions, the user should select the uppermost address bit. If an address bit beyond the selected range is selected, the entire I/O space is allocated to CS0#. For example, if 32 bytes of I/O space are reserved, the active address lines are A[4:0]. To divide this into four regions, the Lower Address CS parameter should be set to A3, by programming the value `0001' into LT2[26:23]. To select two regions, choose A4, and to maintain one region, select any value greater than A4. In 8-bit mode, the memory space block is always 4K bytes, and always divided into four chip-select regions of 1K byte each. In 32-bit mode, again the I/O space can be varied in size from 4 bytes to 256 bytes. It is also possible to increase the memory space block size from 4K bytes to 16K bytes. Also in 32-bit mode, the Lower-Address-CS-Decode parameter afftects division of the I/O space AND memory space into chip-select regions. A soft reset facility is provided so software can independently reset the peripherals on the local bus. The local bus reset signals, LBRST and LBRST#, are always active during a PCI bus reset and also when the configuration register bit LT2[29] is set to 1. The clock enable bit LT2[30], when set enables a copy of the PCI bus clock output on the local bus pin LBCLK. If a reference clock is desired this signal should be used as splitting the PCICLK signal will violate the PCI specification. A buffered crystal clock can also be asserted on the XTL_Ck_Out pin; this means that a single oscillator can be used to drive devices such as UARTs on the local bus. To make use of the XTL_Ck_Out function, a crystal oscillator circuit should be connected to the XTLI and XTLO pins, as shown in Figure 3. XTLO R2 R1 C1 XTLI C2 Figure 3: Crystal Oscillator Circuit Frequency Range (MHz) 1-8 8-60 C1 (pF) 68 33-68 C2 (pF) 22 33 - 68 R1 ( ) 220k 220k-2M2 R2 ( ) 470R 470R Table 8: Component values Note: For better stability use a smaller value of R1. Increase R1 to reduce power consumption. The total capacitive load (C1 in series with C2) should be that specified by the crystal manufacturer (nominally 16pF). Data Sheet Revision 1.22 Page 21 OXFORD SEMICONDUCTOR LTD. OX9160 6 6.1 BIDIRECTIONAL PARALLEL PORT Operation and Mode selection change from open-drain outputs to active push-pull (totem pole) drivers (as required by IEEE 1284) and the pins ACK#, AFD#, BUSY, SLIN# and STB# are redefined as INTR#, DATASTB#, WAIT#, ADDRSTB# and WRITE# respectively. An EPP port access begins with the host reading or writing to one of the EPP port rgisters. The device automatically buffers the data between the I/O registers and the parallel port depending on whether it is a read or a write cycle. When the peripheral is ready to complete the transfer it takes the WAIT# status line high. This allows the host to complete the EPP cycle. If a faulty or disconnected peripheral failed to respond to an EPP cycle the host would never see a rising edge on WAIT#, and subsequently lock up. A built- in time-out facility is provided in order to prevent this from happening. It uses an internal timer which aborts the EPP cycle and sets a flag in the PSR register to indicate the condition. When the parallel port is not in EPP mode the timer is switched off to reduce current consumption. The host time-out period is 10s as specified with the IEEE-1284 specification. The register set is compatible with the Microsoft(R) register definition. Assuming that the upper block is located 400h above the lower block, the registers are found at offset 000-007h and 400-402h. The OX16PCI954 offers a compact, low power, IEEE-1284 (EPP-only) compliant host- interface parallel port, designed to interface to many peripherals such as printers, scanners and external drives. It supports compatibility modes, SPP, NIBBLE and PS2, as well as EPP mode. The register set is compatible with the Microsoft(R) register definition. To enable the parallel port function, the Mode[1:0] pins should be set to `01'. The system can access the parallel port via two 8-byte blocks of I/O space; BAR0 contains the address of the basic parallel port registers, BAR1 contains the address of the upper registers. These are referred to as the `lower block' and `upper block' in this section. If the upper block is located at an address 0x400 above the lower block, generic PC device drivers can be used to configure the port, as the addressable registers of legacy parallel ports always have this relationship. If not, a custom driver will be needed. 6.1.1 SPP mode SPP (output- only) is the standard implementation of a simple parallel port. In this mode, the PD lines always drive the value in the PDR register. All transfers are done under software control. Input must be performed in nibble mode. Generic device driver-software may use the address in I/O space encoded in BAR0 to access the parallel port. The default configuration allocates 8 bytes to BAR0 in I/O space. 6.1.4 ECP mode (not supported) The Extended Capabilities Port `ECP' mode is not supported. 6.1.2 PS2 mode This mode is also referred to as bi-directional or compatible parallel port. In this mode, directional control of the PD lines is possible by setting & clearing DCR[5]. Otherwise operation is similar to SPP mode. 6.2 Parallel port interrupt 6.1.3 EPP mode To use the Enhanced Parallel Port `EPP' the mode bits (ECR[7:5]) must be set to `100'. The EPP address and data port registers are compatible with the IEEE 1284 definition. A write or read to one of the EPP port registers is passed through the parallel port to access the external peripheral. In EPP mode, the STB#, INIT#, AFD# AND SLIN# pins The parallel port interrupt is asserted on INTA#. It is enabled by setting DCR[4]. When DCR[4] is set, an interrupt is asserted on the rising edge of the ACK# (INTR#) pin and held until the status register is read, which resets the INT# status bit (DSR[2]). Data Sheet Revision 1.22 Page 22 OXFORD SEMICONDUCTOR LTD. OX9160 6.3 Register Description The parallel port registers are described below. (NB it is assumed that the upper block is placed 400h above the lower block). Register Name PDR DSR Address Offset 000h 001h 001h 002h 003h 004h 005h 006h 007h 400h 401h 402h 403h R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (EPP mode) (Other modes) R/W R R R/W R/W R/W R/W R/W R/W R/W - SPP (Compatibility Mode) Registers Parallel Port Data Register nBUSY ACK# PE SLCT ERR# INT# nBUSY 0 ACK# 0 PE DIR SLCT ERR# INT# INT_EN nSLIN# INIT# EPP Address Register EPP Data 1 Register EPP Data 2 Register EPP Data 3 Register EPP Data 4 Register Reserved Reserved Reserved - Must write `00001' Reserved 1 1 nAFD# Timeout 1 nSTB# DCR EPPA 1 EPPD1 1 EPPD2 1 EPPD3 1 EPPD4 1 ECR - Mode[2:0] Table 9: Parallel port register set Note 1 : These registers are only available in EPP mode. Note 2 : Prefix `n' denotes that a signal is inverted at the connector. Suffix `#' denotes active-low signalling The reset state of PDR, EPPA and EPPD1-4 is not determinable (i.e. 0xXX). The reset value of DSR is `XXXXX111'. DCR and ECR are reset to `0000XXXX' and `00000001' respectively. 6.3.1 Parallel port data register `PDR' 6.3.2 Device status register `DSR' PDR is located at offset 000h in the lower block. It is the standard parallel port data register. Writing to this register in mode 000 will drive data onto the parallel port data lines. In all other modes the drivers may be tri-stated by setting the direction bit in the DCR. Reads from this register return the value on the data lines. DSR is located at offset 001h in the lower block. It is a read only register showing the current state of control signals from the peripheral. Additionally in EPP mode, bit 0 is set to `1' when an operation times out (see section 6.1.3) DSR[0]: EPP mode: Timeout logic 0 Timeout has not occurred. logic 1 Timeout has occurred (Reading this bit clears it). Other modes: Unused This bit is permanently set to 1. DSR[1]: Unused This bit is permanently set to 1. Data Sheet Revision 1.22 Page 23 OXFORD SEMICONDUCTOR LTD. DSR[2]: INT# logic 0 A parallel port interrupt is pending. logic 1 No parallel port interrupt is pending. This bit is activated (set low) on a rising edge of the ACK# pin. It is de-activated (set high) after reading the DSR. DSR[3]: ERR# logic 0 The ERR# input is low. logic 1 The ERR# input is high. DSR[4]: SLCT logic 0 The SLCT input is low. logic 1 The SLCT input is high. DSR[5]: PE logic 0 The PE input is low. logic 1 The PE input is high. DSR[6]: ACK# logic 0 The ACK# input is low. logic 1 The ACK# input is high. DSR[7]: nBUSY logic 0 The BUSY input is high. logic 1 The BUSY input is low. DCR[3]: nSLIN# logic 0 Set SLIN# output to high (inactive). logic 1 Set SLIN# output to low (active). OX9160 During an EPP address or data cycle the ADDRSTB# pin is driven by the EPP controller, otherwise it is inactive. DCR[4]: ACK Interrupt Enable logic 0 ACK interrupt is disabled. logic 1 ACK interrupt is enabled. DCR[5]: DIR logic 0 PD port is output. logic 1 PD port is input. This bit is overridden during an EPP address or data cycle, when the direction of the port is controlled by the bus access (read/write) DCR[7:6]: Reserved These bits are reserved and always set to "00". 6.3.4 EPP address register `EPPA' 6.3.3 Device control register `DCR' EPPA is located at offset 003h in lower block, and is only used in EPP mode. A byte written to this register will be transferred to the peripheral as an EPP address by the hardware. A read from this register will transfer an address from the peripheral under hardware control. DCR is located at offset 002h in the lower block. It is a read-write register which controls the state of the peripheral inputs and enables the peripheral interrupt. When reading this register, bits 0 to 3 reflect the actual state of STB#, AFD#, INIT# and SLIN# pins respectively. When in EPP mode, the WRITE#, DATASTB# AND ADDRSTB# pins are driven by the EPP controller, although writes to this register will override the state of the respective lines. DCR[0]: nSTB# logic 0 Set STB# output to high (inactive). logic 1 Set STB# output to low (active). During an EPP address or data cycle the WRITE# pin is driven by the EPP controller, otherwise it is inactive. DCR[1]: nAFD# logic 0 Set AFD# output to high (inactive). logic 1 Set AFD# output to low (active). During an EPP address or data cycle the DATASTB# pin is driven by the EPP controller, otherwise it is inactive. DCR[2]: INIT# logic 0 Set INIT# output to low (active). logic 1 Set INIT# output to high (inactive). Data Sheet Revision 1.22 6.3.5 EPP data registers `EPPD1-4' The EPPD registers are located at offset 004h-007h of the lower block, and are only used in EPP mode. Data written or read from these registers is transferred to/from the peripheral under hardware control. 6.3.6 Extended control register `ECR' The Extended control register is located at offset 002h in upper block. It is used to configure the operation of the parallel port. ECR[4:0]: Reserved These bits are reserved and must always be set to "00001". ECR[7:5]: Mode These bits define the operational mode of the parallel port. logic `000' SPP logic `001' PS2 logic `010' Reserved logic `011' Reserved logic `100' EPP logic `101' Reserved logic `110' Reserved logic `111' Reserved Page 24 OXFORD SEMICONDUCTOR LTD. OX9160 7 7.1 SERIAL EEPROM Specification 7.2 EEPROM Data Organisation The OX9160 can be configured using an optional serial Electrically-Erasable Programmable Read Only Memory (EEPROM). If the EEPROM is not present, the device will remain in its default configuration after reset. Although this may be adequate for some applications, many will benefit from the degree of programmability afforded by this feature. The EEPROM interface is based on the 93C46/56 serial EEPROM devices which have a proprietary serial interface known as MicrowireTM. The interface has four pins which supply the memory device with a clock, a chip-select, and serial data input and output lines. In order to read from such a device, a controller has to output serially a read command and address, then input serially the data. The 93C46/56 and compatible devices have a 16-bit data word format but differ in memory size (and number of address bits). The OX9160 incorporates a controller module which reads data from the serial EEPROM and writes data into the configuration register space. It performs this operation in a sequence which starts immediately after a PCI bus reset and ends either when the controller finds no EEPROM is present or when it reaches the end of its data. The operation of this controller is described below. Following device configuration, driver software can access the serial EEPROM through four bits in the device-specific Local Configuration Register LCC[27:24]. Software can use this register to manipulate the device pins in order to read and modify the EEPROM contents. The OX9160 requires a total of bytes of EEPROM data to program all the EEPROM writable registers. The 93C46 and 93C56 EEPROM devices offer 128 and 256 bytes of programmable data respectively. A Windows(R) based utility to program the EEPROM is available. For further details please contact Oxford Semiconductor (see back cover). MicrowireTM is a trade mark of National Semiconductor. For a description of MicroWire, please refer to National Semiconductor data manuals. The serial EEPROM data is divided in four zones. The size of each zone is an exact multiple of 16-bit WORDs. Zone0 is allocated to the header. A valid EEPROM program must contain a header. The EEPROM can be programmed from the PCI bus. Once the programming is complete, the device driver should either reset the PCI bus or set LCC[29] to reload the OX9160 registers from the serial EEPROM. The general EEPROM data structure is shown in Table 10. DATA Zone 0 1 2 3 Size (Words) One One or more Two Two or more Description Header Local Configuration Registers Identification Registers PCI Configuration Registers Table 10: EEPROM data format 7.2.1 Zone0: Header The header identifies the EEPROM program as valid. Bits 15:4 Description These bits should return 0x950 to identify a valid program. Once the OX9160 reads 0x950 from these bits, it sets LCC[28] to indicate that a valid EEPROM program is present. Reserved. Write `0' to this bit. 1 = Zone1 (Local Configuration) exists 0 = Zone1 does not exist 1 = Zone2 (Identification) exists 0 = Zone2 does not exist 1 = Zone3 (PCI Configuration) exists 0 = Zone3 does not exist 3 2 1 0 The programming data for each zone follows the proceeding zone if it exists. For example a Header value of 0x9507 indicates that all zones exist and they follow one another in sequence, while 0x9505 indicates that only Zones 1 and 3 exist where the header data is followed by Zone1 WORDs, and since Zone2 is missing Zone1 WORDs are followed by Zone3 WORDs. Data Sheet Revision 1.22 Page 25 OXFORD SEMICONDUCTOR LTD. OX9160 7.2.2 Zone1: Local Configuration Registers Bits 15 Description `0' = There are no more Configuration WORDs to follow in Zone1. Move to the next available zone or end EEPROM program if no more zones are enabled in the Header. `1' = There is another Configuration WORD to follow for the Local Configuration Registers. These seven bits define the byte-offset of the Local configuration register to be programmed. For example the byte-offset for LT2[23:16] is 0x0E. 8-bit value of the register to be programmed Table 11: Zone 1 data format The Zone1 region of EEPROM contains the program value of the vendor-specific Local Configuration Registers using one or more configuration WORDs. Registers are selected using a 7-bit byte-offset field. This offset value is the offset from Base Address Registers in I/O or memory space (see section 1.1). Note: Not all of the registers in the Local Configuration Register set are writable by EEPROM. If bit2 of the header is set, Zone1 configuration WORDs follow the header declaration. The format of configuration WORDs for the Local Configuration Registers in Zone1 are described in Table 11. 14:8 7:0 Table 12 shows which Local Configuration registers are writable from the EEPROM. Note that an attempt by the EEPROM to write to any other offset locations can result in unpredictable behaviour. Offset 0x00 0x00 0x00 0x00 0x00 0x04 0x05 0x06 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0E 0x0E 0x0F 0x0F 0x0F 0x0F 0x0F 0x1E 0x1E 0x1F Bits 1:0 2 4:3 6:5 7 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 3:0 6:4 7 2:0 4:3 5 6 7 4 7:5 7:0 Description Must be `00'. Enable crystal clock output. Endian byte-lane select. Power-down filter. MIO2_PME enable. Multi-purpose IO configuration. Multi-purpose IO configuration. Multi-purpose IO configuration. Local bus timing parameters Local bus timing parameters Local bus timing parameters Local bus timing parameters Local bus timing parameters Local bus timing parameters Must be `0000'. IO Space Block size. Lower-Address-CS-Decode. Lower-Address-CS-Decode. Memory space block size in 32-bit Local bus. Must be `0'. Local bus clock enable. Bus interface type. MIO0/Parallel Port interrupt mask Multi-purpose IO interrupt mask. Multi-purpose IO interrupt mask. Reference LCC[2] LCC[4:3] LCC[6:5] LCC[7] MIC[7:0] MIC[15:8] MIC[23:16] LT1[7:0] LT1[15:8] LT1[23:16] LT1[31:24] LT2[7:0] LT2[15:8] LT2[22:20] LT2[23] LT2[26:24] LT2[28:27] LT2[30] LT2[31] GIS[20] GIS[23:21] GIS[31:24] Table 12: EEPROM-writable Local Configuration Registers Data Sheet Revision 1.22 Page 26 OXFORD SEMICONDUCTOR LTD. OX9160 7.2.3 Zone2: Identification Registers Bits 15 14:8 The Zone2 region of EEPROM contains the program value for Vendor ID and Subsystem Vendor ID. The format of Device Identification configuration WORDs are described in Table 13. Bits 15 Description `0' = There are no more Zone2 (Identification) bytes to program. Move to the next available zone or end EEPROM program if no more zones are enabled in the Header. `1' = There is another Zone1 (Identification) byte to follow. 0x00 = Vendor ID bits [7:0]. 0x01 = Vendor ID bits [15:8]. 0x02 = Subsystem Vendor ID [7:0]. 0x03 = Subsystem Vendor ID [15:8]. 0x03 to 0x7F = Reserved. 8-bit value of the register to be programmed Table 13: Zone 2 data format 7:0 Description `0' = This is the last configuration WORD. `1' = There is another WORD to follow for this function. These seven bits define the byte-offset of the PCI configuration register to be programmed. For example the byte-offset of the Extended Capabilities register is 0x06. Offset values are tabulated in section 4.2. 8-bit value of the register to be programmed Table 14: Zone 3 data format (data) 14:8 Table 15 shows which PCI Configuration registers are writable from the EEPROM. Offset 0x02 0x03 0x06 0x06 0x06 0x09 0x0A 0x0B 0x2E 0x2F 0x42 0x43 Bits 7:0 7:0 3:0 4 7:5 7:0 7:0 7:0 7:0 7:0 7:0 7:0 Description Device ID bits 7 to 0. Device ID bits 15 to 8. Must be `0000'. Extended Capabilities. Must be `000'. Class Code bits 7 to 0. Class Code bits 15 to 8. Class Code bits 23 to 16. Subsystem ID bits 7 to 0. Subsystem ID bits 15 to 8. Power Management Capabilities bits 7 to 0. Power Management Capabilities bits 15 to 8. 7:0 7.2.4 Zone3: PCI Configuration Registers The Zone3 region of EEPROM contains any changes required to the PCI Configuration registers (with the exception of Vendor ID and Subsystem Vendor ID which are programmed in Zone2). This zone consists of a function header WORD, one or more configuration WORDs, and a function end WORD. The function header WORD is defined as 0x8001, and the end WORD is defined as 0x0000. The data between the function header WORD and the end WORD consists of one or more configuration WORDs, which contain the address offset and a byte of data for the PCI Configuration Space of the function. The format of configuration WORDs for the PCI Configuration Registers are described below. Table 15: EEPROM-writable PCI configuration registers Table 16 shows an example zone 3 which sets the device ID with two configuration words. Description Function header word Set Device ID[7:0] - one more config word Set Device ID[15:8] - no more config words end WORD Table 16: Example zone 3 data Data 0x8001 0x82CD 0x03AB 0x0000 Data Sheet Revision 1.22 Page 27 OXFORD SEMICONDUCTOR LTD. OX9160 8 OPERATING CONDITIONS Symbol VDD VIN IIN T STG Parameter DC supply voltage DC input voltage DC input current Storage temperature Table 17: Absolute maximum ratings Symbol VDD TC TI Parameter DC supply voltage Commercial temperature Industrial temperature Min 4.5 0 -40 Max 5.5 70 85 Units V C C Min -0.3 -0.3 -40 Max 7.0 VDD + 0.3 +/- 10 125 Units V V mA C Table 18: Recommended operating conditions 9 9.1 DC ELECTRICAL CHARACTERISTICS Non-PCI I/O Buffers Symbol VDD VIH VIL CIL COL IIH IIL VOH VOH VOL VOL IOZ Symbol ICC Parameter Supply voltage Input high voltage Input low voltage Cap of input buffers Cap of output buffers Input high leakage current Input low leakage current Output high voltage Output high voltage Output low voltage Output low voltage 3-state output leakage current Condition Commercial TTL Interface 1 TTL Schmitt trig TTL Interface 1 TTL Schmitt trig Min 4.75 2.0 2.0 Max 5.25 0.8 0.8 5.0 10.0 10 10 Units V V V pF pF A A V V V V A Units mA Vin = VDD Vin = VSS IOH = 1 A IOH = 4 mA 2 IOL = 1 A IOL = 4 mA 2 VDD - 0.05 -10 -10 2.4 -10 Typical 35 2 0.05 0.4 10 Max 48.1 34.4 Parameter Operating supply current in normal mode Operating supply current in Power-down mode Table 19: Characteristics of non-PCI I/O buffers Note 1: Note 2: All input buffers are TTL with the exception of PCI buffers IOH and IOL are 12 mA for PD/LBDB[7:0] and other Parallel Port Outputs. They are 4 mA for all other non-PCI outputs Data Sheet Revision 1.22 Page 28 OXFORD SEMICONDUCTOR LTD. OX9160 9.2 PCI I/O Buffers Condition Min 4.75 -0.5 2.0 VIN = 0.5V VIN = 2.7V IOUT = -2 mA IOUT = 3 mA, 6mA Max 5.25 0.8 VCC + 0.5 -70 70 0.55 10 12 8 10 Unit V V V A A V V pF pF pF nH Symbol Parameter DC Specifications VCC Supply voltage VIL Input low voltage VIH Input high voltage IIL Input low leakage current IIH Input high leakage current VOL Output low voltage VOH Output low voltage CIN Input pin capacitance CCLK CLK pin capacitance CIDSEL IDSEL pin capacitance LPIN Pin inductance AC Specifications Switching current IOH(AC) high (Test point) Switching current low (Test point) Low clamp current High clamp current Output rise slew rate Output fall slew rate 2.4 5 IOL(AC) ICL IHL SlewR SlewF 0 < VOUT 1.4 1.4 < VOUT 2.4 3.1 < VOUT VCC VOUT = 3.1 VOUT 2.2 2.2 > VOUT > 0.55 0.71 > VOUT > 0 VOUT = 0.71 -5 < VIN < -1 VCC+4 < VIN VCC+1 0.4V to 2.4V 2.4V to 0.4V < -44 -44 (VOUT - 1.4)/0.024 Eq. A -142 mA 95 VOUT / 0.023 mA Eq. B 206 -25 + (VIN +1)/ 0.015 25+ (VIN -VCC -1)/ 0.015 1 1 mA mA 5 5 V/nS V/nS Table 20: Characteristics of PCI I/O buffers Eq. A : Eq. B : IOH = 11.9 * (VOUT - 5.25) * (VOUT + 2.45) IOL = 78.5 * VOUT * (4.4 - VOUT ) for 3.1 < VOUT VCC for 0.71 > VOUT > 0 Data Sheet Revision 1.22 Page 29 OXFORD SEMICONDUCTOR LTD. OX9160 10 AC ELECTRICAL CHARACTERISTICS 10.1 PCI Bus The timings for PCI pins comply with PCI Specification for the 5.0 Volt signalling environment. 10.2 Local bus By default, the Local bus control signals change state in the cycle immediately following the reference cycle, with offsets to provide setup and hold times for common peripherals in Intel mode. The tables below show these default values; however each of these can be increased or decreased by an number of PCI clock cycles by adjusting the parameters in registers LT1 and LT2. Symbol tref tza tard tzrcs1 tzrcs2 tcsrd trdcs tzrd1 tzrd2 tdrd tzd1 tzd2 tsd thd Parameter IRDY# falling to reference LBCLK Reference LBCLK to Address Valid Address Valid to LBRD# falling Reference LBCLK to LBCS# falling Reference LBCLK to LBCS# rising LBCS# falling to LBRD# falling LBRD# rising to LBCS# rising Reference LBCLK to LBRD# falling Reference LBCLK to LBRD# rising Data bus floating to LBRD# falling Reference LBCLK to data bus floating at the start of the read transaction Reference LBCLK to data bus driven by OX9160 at the end of the read transaction Data bus valid to LBRD# rising Data bus valid after LBRD# rising Table 21: Read operation from Intel-type Local bus Min Max Units Nominally 2 PCI clock cycles TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD TBD TBD TBD TBD ns ns ns Symbol tref tza tawr tzwcs1 tzwcs2 tcswr twrcs tzwr1 tzwr2 tzdv tzdf twrdi Parameter IRDY# falling to reference LBCLK Reference LBCLK to Address Valid Address Valid to LBWR# falling Reference LBCLK to LBCS# falling Reference LBCLK to LBCS# rising LBCS# falling to LBWR# falling LBWR# rising to LBCS# rising Reference LBCLK to LBWR# falling Reference LBCLK to LBWR# rising Reference LBCLK to data bus valid Reference LBCLK to data bus high-impedance LBWR# rising to data bus invalid Table 22: Write operation to Intel-type Local bus Min Max Units Nominally 2 PCI clock cycles TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns Data Sheet Revision 1.22 Page 30 OXFORD SEMICONDUCTOR LTD. OX9160 Symbol tref tza tads tzrds1 tzrds2 vtdrd tzd1 tzd2 tsd thd Parameter IRDY# falling to reference LBCLK Reference LBCLK to Address Valid Address Valid to LBDS# falling Reference LBCLK to LBDS# falling Reference LBCLK to LBDS# rising Data bus floating to LBDS# falling Reference LBCLK to data bus floating at the start of the read transaction Reference LBCLK to data bus driven by OX9160 at the end of the read transaction Data bus valid to LBDS# rising Data bus valid after LBDS# rising Min Max Units Nominally 2 PCI clock cycles TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD TBD TBD TBD TBD ns ns ns Table 23: Read operation from Motorola-type Local bus Symbol tref tza tads tzw1 tzw2 twds tdsw tzwds1 tzwds2 tzdv tzdf tdsdi Parameter IRDY# falling to reference LBCLK Reference LBCLK to Address Valid Address Valid to LBDS# falling Reference LBCLK to LBRDWR# falling Reference LBCLK to LBRDWR# rising LBRDWR# falling to LBDS# falling LBDS# rising to LBRDWR# rising Reference LBCLK to LBDS# falling Reference LBCLK to LBDS# rising Reference LBCLK to data bus valid Reference LBCLK to data bus high-impedance LBDS# rising to data bus invalid Min Max Units Nominally 2 PCI clock cycles TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns Table 24: Write operation to Motorola-type Local bus Data Sheet Revision 1.22 Page 31 OXFORD SEMICONDUCTOR LTD. OX9160 11 TIMING WAVEFORMS CLK 1 2 3 4 FRAME# AD[31:0] C/BE[3:0]# IRDY# TRDY# DEVSEL# STOP# Address Bus CMD Data Byte enable# Data transfer 1 2 3 4 Figure 4: PCI Read transaction from Local Configuration registers CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# TRDY# DEVSEL# STOP# Address Bus CMD Data Byte enable# Data transfer Figure 5: PCI Write transaction to Local Configuration Registers Data Sheet Revision 1.22 Page 32 OXFORD SEMICONDUCTOR LTD. OX9160 TIMING WAVEFORMS CLK 1 2 3 4 5 n+5 n+6 Where: n = 0, 1, .., 9 n+7 FRAME# AD[31:0] C/BE[3:0]# IRDY# Wait Wait Wait Address Bus CMD Data Byte enable# Data TRDY# DEVSEL# STOP# LBCLK LBA Local Bus Reference Cycle t ref t za t ard Valid Local Bus Address t zrcs2 trdcs Data sampled LBCS# LBRD# LBD LBD 1 t zrcs1 t csrd tzrd1 t t zd1 drd tzrd2 t zd2 Valid Data t sd Valid Data 2 t hd Figure 6: PCI Read Transaction from Intel-type Local bus Data Sheet Revision 1.22 Data transfer Wait Page 33 OXFORD SEMICONDUCTOR LTD. OX9160 TIMING WAVEFORMS CLK 1 2 3 4 5 n+5 n+6 n+7 Where: n = 0, 1, .., 9 FRAME# AD[31:0] C/BE[3:0]# IRDY# Wait Wait Wait Address Bus CMD Data Byte enable# TRDY# DEVSEL# STOP# LBCLK LBA Local Bus Reference Cycle t ref t za ta w r Valid Local Bus Address tzwcs2 twrcs tzwr2 LBCS# LBWR# LBD LBD 1 t zwcs1 tc s w r tzwr1 Valid Local Bus Data t zdv Valid Local Bus Data twrdi t zdf 2 Figure 7: PCI Write Transaction to Intel-type Local bus Data Sheet Revision 1.22 Data transfer Wait Page 34 OXFORD SEMICONDUCTOR LTD. OX9160 TIMING WAVEFORMS CLK 1 2 3 4 5 n+5 n+6 Where: n = 0, 1, .., 9 n+7 FRAME# AD[31:0] C/BE[3:0]# IRDY# Wait Wait Wait Address Bus CMD Data Byte enable# Data TRDY# DEVSEL# STOP# LBCLK LBA LBRDWR# LBDS# LBD LBD 1 Local Bus Reference Cycle t ref t za t ads Valid Local Bus Address t zd1 tdrd Data sampled tzrds1 tzrds2 Data transfer Wait t zd2 Valid Data t sd Valid Data 2 t hd Figure 8: PCI Read Transaction from Motorola-type Local bus Data Sheet Revision 1.22 Page 35 OXFORD SEMICONDUCTOR LTD. OX9160 TIMING WAVEFORMS CLK 1 2 3 4 5 n+5 n+6 n+7 Where: n = 0, 1, .., 9 FRAME# AD[31:0] C/BE[3:0]# IRDY# Wait Wait Wait Address Bus CMD Data Byte enable# TRDY# DEVSEL# STOP# LBCLK LBA Local Bus Reference Cycle t ref t za t ads Valid Local Bus Address t zw2 t dsw t zw1 LBRDWR# LBDS# LBD LBD 1 t wds t zwds1 t zwds2 Valid Local Bus Data t zdv Valid Local Bus Data tdsdi t zdf 2 Figure 9: PCI Write Transaction to Motorola-type Local bus Data Sheet Revision 1.22 Data transfer Wait Page 36 OXFORD SEMICONDUCTOR LTD. OX9160 12 PACKAGE INFORMATION Figure 10: 160 pin Thin Quad Flat Pack (TQFP) package 13 ORDERING INFORMATION OX9160-TQC33-A Revision Package Type - 160 TQFP Data Sheet Revision 1.22 Page 37 OXFORD SEMICONDUCTOR LTD. OX9160 CONTACT DETAILS Oxford Semiconductor Ltd. 25 Milton Park Abingdon Oxfordshire OX14 4SH United Kingdom Telephone: Fax: Sales e-mail: Web site: +44 (0)1235 824900 +44 (0)1235 821141 sales@oxsemi.com http://www.oxsemi.com DISCLAIMER Oxford Semiconductor believes the information contained in this document to be accurate and reliable. However, it is subject to change without notice. No responsibility is assumed by Oxford Semiconductor for its use, nor for infringement of patents or other rights of third parties. No part of this publication may be reproduced, or transmitted in any form or by any means without the prior consent of Oxford Semiconductor Ltd. Oxford Semiconductor's terms and conditions of sale apply at all times. Data Sheet Revision 1.22 Page 38 |
Price & Availability of OX9160
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |